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november 2010 doc id 14273 rev 3 1/29 1 L9758 multiple supply for engine control features buck converter pre-regulated supply rated for a minimum of 2 a (rms) optional boost converter for low battery conditions 5 v, 2% @ 1 a, v dd5 low dropout (ldo) regulator programmable 3.3 v or 2.6 v, 2% @ 1 a, v ddl ldo regulator with external pass transistor programmable microcontroller core voltage ldo regulator, v core 2% @ 1 a with external voltage divider and pass transistor programmable 1 v or 1.5 v, 10% @ 10 ma, standby memory regulator (v kam ) programmable 3.3 v or 2.6 v, 10% @ 10 ma alternate standby regulator (vstby) four 5 v 7 mv @ 50 ma protected tracking regulators, one of them with selectable external voltage reference. independent reset signals, rst5 and rstl for the v dd5 , v ddl supplies. independent standby voltage monitor standby_ok two power supply enable signals for different voltage level signals battery voltage thresholding - ign logic level thresholding - psu_en description the L9758 is a multiple output voltage regulator utilizing linear, switchmode (buck and boost) and tracking regulators to support high end automotive microcontrollers used in powertrain applications. the L9758 provides two standby power regulators as well as controllable ldo regulators. the L9758 has power on reset functionality and controlled slew rate of the v dd5 , v ddl and v core . powerso-36 table 1. device summary order code temperature range package packing L9758 -40 c to +125 c powerso-36 tube www.st.com
contents L9758 2/29 doc id 14273 rev 3 contents 1 pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 general dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 buck pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 boost pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 vdd5 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 vddl linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 vcore linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 vkam linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 vstby linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9 vsa, vsb, vsc, vsd tracking linear regulator . . . . . . . . . . . . . . . . . . . . 18 4.10 rst5 and rstl reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11 ign and psu_en inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12 stby_ok signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 general function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 switching pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 vdd5, vddl and vcore linear regulators . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 tracking regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 vkam and vstby linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.6 reset monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.7 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.8 reference current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
L9758 contents doc id 14273 rev 3 3/29 6 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2.1 entry into run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 low voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5 high voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
list of tables L9758 4/29 doc id 14273 rev 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. control pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. general dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. buck pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. boost pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. vdd5 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. vddl linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12. vcore linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13. vkam linear regula tor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14. vstby linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15. vsa, vsb, vsc, vsd tracking linea r regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 16. rst5 reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 17. rstl reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 18. ign and psu_en inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 19. stby_ok signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 20. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L9758 list of figures doc id 14273 rev 3 5/29 list of figures figure 1. pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. current reference generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. power up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5. powerso-36 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
pins configuration L9758 6/29 doc id 14273 rev 3 1 pins configuration figure 1. pins connection (top view) table 2. pins description pin # name description 1 gnd power ground 2 vbat battery power source 3 vbat_sw switched battery power source 4 boost external boost transistor predriver output 5 res_s boost (+) curre nt comparator input 6 gnd_s boost (-) current comparator input 7 vbat_s battery feedback for boost controller 8 ign ignition switch 9 ign_on ignition state 10 psu_en power supply enable 11 vsd tracking regulator d 12 vsc tracking regulator c 13 vsb tracking regulator b 14 vsa tracking regulator a 15 track_ref tracking a voltage reference gnd vbat vbat_sw boost res_s vbat_s gnd_s ign ign_on 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 psu_en vsd vsc vsb vsa track_ref ref_sel vs_dis rext sw fdbk vb vdd5 vddl_drv vddl_fdbk vcore_fdbk vcore_drv core_dis vprog3 vprog1 vprog2 vkam vstby stby_ok rst5 rstl rst_tim
L9758 pins configuration doc id 14273 rev 3 7/29 16 ref_sel tracking a voltage reference selection 17 vs_dis sensor supply disable 18 rext external current reference resistance 19 rst_tim reset timer adjustment 20 rstl vddl regulator reset output 21 rst5 vdd5 regulator reset output 22 stby_ok standby regulator monitor 23 vstby standby regulator output 24 vkam standby memory regulator output 25 vprog2 standby regulator voltage selection (vstby) 26 vprog1 standby memory regulator voltage selection (vkam) 27 core_dis vddl and vcore disable 28 vprog3 vddl voltage selection 29 vcore_drv vcore external pass transistor predriver output 30 vcore_fdbk vc ore feedback 31 vddl_fdbk vddl feedback 32 vddl_drv vddl external pass transistor predriver output 33 vdd5 vdd5 linear regulator output 34 vb switching preregulator output 35 fdbk switching voltage feedback 36 sw buck regulator switch output table 3. control pins description pin name logic level description type of i/o ign low enter in stand-by mode if also psu_en is low pull down high enter in run mode ign_on low ign is high open drain high ign is low psu_en low enter in stand-by mode if also ign is low pull down high enter in run mode vs_dis low enable vsb, vsc, vsd tracking regulators pull down high disable vsb, vsc, vsd tracking regulators ref_sel low voltage reference for vsa tracking regulator is vdd5 pull down high voltage reference for vsa tracking regulator is vtrack_ref table 2. pins description (continued) pin # name description
pins configuration L9758 8/29 doc id 14273 rev 3 rstl low vddl output regulator out of range (under voltage) open collector high vddl output regulator fully operational rst5 low vdd5 output regulator out of range (under voltage) open collector high vdd5 output regulator fully operational vprog1 low vkam regulator output programmed to 1v pull up high vkam regulator output programmed to 1.5v vprog2 low vstby regulator output programmed to 2.6v pull up high vstby regulator output programmed to 3.3v vprog3 low vdll regulator output programmed to 2.6v pull up high vdll regulator output programmed to 3.3v core_dis low enable vdll and vcore linear regulators pull down high disable vdll and vcore linear regulators stby_ok low vstby output regulator out of range (under voltage) open drain high vstby output regulator fully operational table 3. control pins description (continued) pin name logic level description type of i/o
L9758 functional block diagram doc id 14273 rev 3 9/29 2 functional block diagram figure 2. functional block diagram linear voltage controller linear voltage controller vddl vcore analog mux linear voltage regulator vdd5 tracking regulator tracking regulator tracking regulator vsc tracking regulator vsa vsb vsd boost control smps osc. (5 mhz) band gap ref. charge pump buck switchmode power supply oscillator / divider power up/dn vkam vreg 1v/1.5v, 10ma 2.6v/3.3v, 10ma stby vreg bandgap 1.5v, 1.0a 2.5v / 3.5v, 1.0a 5v, 1.0a 50ma 50ma 50ma reset logic open drain soft start en_reg soft start 50ma en_reg en_reg vprog1 vbat vprog2 vbat_s boost res_s gnd_s vbat_sw rext vprog3 rst_tim core_dis track_ref ref_sel vs_dis ign psu_en gnd 10f 2.2f 2.2f 2.2f 1 f 1 f 22 f 22 h 2.4k 5.1k 0.1 22 h 300f 10 f 100 nf vstby stby_ok vkam sw fdbk vb vddl_fdbk vcore_drv vddl_drv rst5 rstl 51k rtim vdd5 vsa vsc vsb 22 uf 22 uf vsd ign_on 2.2f vddl undervoltage vdd5 undervoltage power on reset 10k vbat stby vbat run vcore_fdbk vcore_fdbk vddl
operating conditions L9758 10/29 doc id 14273 rev 3 3 operating conditions 3.1 absolute maximum ratings this part may be irreparably damaged if taken outside the specified absolute maximum ratings. operation above the absolute maximum ratings may also cause a de crease in reliability. warning: exceeding these values might destroy this part. this part is not guaranteed to function properly at these ratings. the cmos inputs and outputs should never go above 5v + 0.3v or below gnd - 0.3v without protection (series resistance). if this occurs, the device might be destroyed by latch-up and/or the output levels might not be controlled by the inputs. unused inputs must be connected to gnd and unused outputs should be left open and programmed to a low state. unused i/o pins should be programmed as outputs, left open, and programmed to a low state. table 4. absolute maximum ratings symbol parameter value unit vbat,v bat_sw , v bat_s battery supply voltage -0.3 to 40 v v ign ignition input voltage (with at least 10k external resistance) -2.0 to 40 v v i-digital digital input voltages ( psu_en, vs_en, vprog1, vprog2, vprog3, vddl/vcore_en, ref_sel) -0.3 to 7 v v i-analog analog input voltages (rext, track_ref, rst_tim vddl_fdbk, vcore_fdbk) -0.3 to 7 v v b linear regulator supply (vb) -0.3 to 40 v v fdbk switching feedback (fdbk) -0.3 to 40 v v sw buck regulator switch output (sw) -2 to 40 v v o-digital digital output voltages (ign_on, rstl, rst5, boost, stby_ok) -0.3 to 7 v v or regulator output voltages (v dd5, vstby, vkam) -0.3 to 7 v v vsx regulator output voltages (vsa, vsb, vsc, vsd) -3 to 40 v v core_drv , v ddl_drv external regulator predriver output (vcore_drv, vddl_drv) -0.3 to 15 v i smps switching preregulator current 0 to 4.2 a t op operating temperature -40 to 125 c t stg storage temperature -50 to 150 c t j max junction temperature 150 c v esd max esd (human body model) 2 kv
L9758 operating conditions doc id 14273 rev 3 11/29 3.2 operating ranges full specification parameters cannot be guaranteed outside the operating ranges. once the condition is returned to within the specifi ed operating ranges, the part will recover with no damage or degradation. 3.3 thermal data table 5. operating ranges symbol parameter value unit v bat , v bat_sw , v bat_s battery supply voltage 4 to 26.5 v 4 to 40 (t < 400ms) v ign ignition input voltage (with at least 10k external resistance) 4 to 26.5 v v i-digita l digital input voltages (psu_en,vs_en,vprog1, vprog2, vprog3, vddl/vcore_en, ref_sel) -0.3 to 5.3 v v i-analog analog input voltages (rext, track_ref, rst_tim vddl_fdbk, vcore_fdbk) -0.3 to 5.3 v i ave switching preregulator average current 0 to 2.5 a t op operating temperature -40 to 125 c t j junction temperature -40 to 150 c table 6. thermal data symbol parameter value unit r th(j-case) thermal resistance junction-to-case 2 c/w
electrical characteristics L9758 12/29 doc id 14273 rev 3 4 electrical characteristics all voltage values are, if not otherwise stated, relative to ground.current flow into a pin is positive. if not otherwise stated, all rise times are between 10% and 90%, fall times between 90% and 10% and delay times at 50% of the relevant steps. 4.1 general dc characteristics t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v, unless otherwise specified. table 7. general dc characteristics symbol parameter test condition min. typ. max. unit i bat_sw_sb quiescent current at pin bat_sw v bat = 0 v; v bat_sw = 12 v i q_off supply current in off state i vbat_sw + i vbat --120a v lv i _ l ow low voltage inhibit low threshold -3.5-3.9v v lv i _ h i g h low voltage inhibit high threshold -4.0-4.5v v lv i _ h y s low voltage inhibit hysteresis -0.3-1v v st linear start-up voltage - 3.8 - 4.8 v v rext rext voltage - 1.18 - 1.24 v v th_vsen vs_en input threshold - 0.8 - 2 v v vddl/vcore_en vddl/vcore_en input threshold -0.8-2v v prog1_low prog1 input low voltage ---0.8v v prog2_low prog2 input low voltage ---0.8v v prog3_low prog3 input low voltage ---0.8v v ddl_enup vddl power-up enable - 1 - 2 v
L9758 electrical characteristics doc id 14273 rev 3 13/29 4.2 buck pre-regulator t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v; unless otherwise specified. table 8. buck pre-regulator symbol parameter test cond ition min. typ. max. unit f sw operating frequency r ext = 10.0 kohm 1% v bat_sw = 13.5 v 300 - 450 khz r dson high side switch on resistance v bat_sw = 6.0v - - 0.25 i st_max average current during start-up v b = 3.0v 0.3 - 0.7 a v breg output voltage 7.0v < v bat_sw < 18v 0.25a < i vbat <2.0a 5.5 - 6.1 v vb100 100% duty cycle operation threshold voltage sensed at vbat_sw pin 6.2 - 7.8 v vb100h 100% duty cycle operation threshold hysteresis 0.05 - 0.8 v vpre load regulation i vb = 0.1a ?2a v bat_sw = 13.5v - - 400 mv vrpre voltage ripple, p-p l = 22h, c = 22f x7r v bat_sw = 13.5v --300mv ts start time l = 22h, c = 22f x7r - - 1.4 ms dcmin minimum duty cycle - 10 - 18 % eff efficiency v bat_sw = 13.5 v i vb = 0.5a v bat_sw = 13.5v i vb = 2a 70 70 -- % l rs output inductance - 15 22 30 75 h m c esr output capacitance - 10 0 - 100 160 f m ov power-up overvoltage v bat_sw < 26.5v 0.25a < i vbat <2.0a 15 - 200 mv tr _ sw tf_sw sw rising and falling time 7.0v < v bat_sw < 18v i vbat <2.0a (20%, 80%) 10 - 150 s
electrical characteristics L9758 14/29 doc id 14273 rev 3 4.3 boost pre-regulator t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v, unless otherwise specified. table 9. boost pre-regulator symbol parameter test condition min. typ. max. unit fsw operating frequency r ext = 10.0 kohm 1% v bat_sw = 13.5 v 300 - 450 khz v b_reg output voltage 4.0 v < v bat_s < 7 v, 0.25 a < i vb < 2.0 a 8.5 - 10 v boostonth boost enable threshold voltage sensed at vbat_s pin 7.0 - 8.3 v boostoffth boost disable threshold 7.0 - 8.3 v v boost_hy boost operation threshold hysteresis voltage sensed at vbat_s pin 0.05 - 0.9 v v boost load regulation i vb = 0.1 a?2 a v bat_s = 4 v - - 600 mv v r_vboost voltage ripple, p-p l = 22 h, c = 300 f x7rx7r v bat_s = 4 v - - 600 mv v olb boost predriver low level voltage i sink = 1 ma - - 0.2 v v ohb boost predriver low level voltage i source = 200 a 4.8 - - v t rb boost predriver rise time cl = 1 nf 50 - 180 ns t fb boost predriver fall time cl = 1 nf 20 - 100 ns l rs output inductance - 15 22 30 75 h m c esr output capacitance - 100 10 300 900 200 f m r sense sensing resistor - 40 50 - m
L9758 electrical characteristics doc id 14273 rev 3 15/29 4.4 vdd5 linear regulator t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v, unless otherwise specified. 4.5 vddl linear regulator t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v, unless otherwise specified. table 10. vdd5 linear regulator symbol parameter test condition min. typ. max. unit v dd5 output voltage 5 ma < i dd5 < 1 a v bat_sw => 5.7 v 5 ma < i dd5 < 800 ma v bat_sw = 5.5 v 5 ma < i dd5 < 1 a v bat_sw 4 v 4.9 3.3 - 5.1 4.0 v i dd5_lim current limit v dd5 = 4.75 v 1200 - 2500 ma c dd5 esr output capacitor ceramic or tantalum c = 4.7f 4.7 0 - 100 160 f m r rdd5 ripple rejection f = 375 khz 26 - - db v dd5_max maximum overshoot vb/ t < 70 v/ms v bat_sw = 4v ? 8 v --5.5v v dd5 / t output voltage slew rate at power-up 5 ma < i dd5 < 1 a v bat_sw = 13.5 v 10 - 20 v/ms i dd5 load current - 5 - 1000 ma v dd5 liner line regulation 6.0 v < v b < 7 v -25 - +25 mv v dd5 loadr load regulation 5 ma < i dd5 < 1 a -25 - +25 mv v dd5 -v ddl start up v dd5 -v ddl during start up 0.5 - 3.1 mv table 11. vddl linear regulator symbol parameter test condition min. typ. max. unit v ddl output voltage 5 ma < i ddl < 1 a, v prog3 = open 4.0 v < v bat_sw < 18 v 5 ma electrical characteristics L9758 16/29 doc id 14273 rev 3 4.6 vcore linear regulator t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v, unless otherwise specified. v ddl_max maximum overshoot 5 ma L9758 electrical characteristics doc id 14273 rev 3 17/29 4.7 vkam linear regulator t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v, unless otherwise specified. 4.8 vstby linear regulator t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v, unless otherwise specified. table 13. vkam linear regulator symbol parameter test condition min. typ. max. unit v kam output voltage 0.1ma < i vkam < 10ma, v prog1 = low 4.0v < v bat < 18v 0.1ma < i vkam < 10ma, v prog1 =open 4.0v < v bat < 18v 0.9 1.37 - 1.1 1.65 v c vkam esr output capacitor ceramic 0.1 0 - 4.7 20 f m rr vkam ripple rejection f=375 khz 26 - db v kam_m maximum overshoot (absolute value relative to gnd) 0.1 ma < i vkam < 10 ma, v prog1 = low 4v < v bat < 18 v 0.1 ma < i vkam < 10 ma, v prog1 =open 4v < v bat < 18 v -- 1.2 1.7 v iddkamsh current limit v kam = 0.5 v 11 - 50 ma i kam load current - 0.1 - 10 ma v kam liner line regulation 6 v < v bat < 18 v -25 - +25 mv v kam loadr load regulation 0.1 ma < i kam < 10 ma -25 - +25 mv table 14. vstby linear regulator symbol parameter test condition min. typ. max. unit v stby output voltage 0.1 ma < i stby < 10 ma, v prog2 = low 4 v < v bat < 18 v 0.1 ma < i stby < 10 ma, v prog2 = open 4 v < v bat < 18 v 2.47 3.13 - 2.73 3.47 v c stby esr output capacitor ceramic 0.1 0 - 10 20 f m rr stby ripple rejection f = 350 khz 26 - - db v stby_m maximum overshoot (absolute value relative to gnd) 0.1 ma < i stby < 10 ma, v prog2 = low 4 v < v bat < 18 v 0.1 ma < i stby < 10 ma, v prog2 = open 4 v < v bat < 18 v -- 3.05 3.75 v i stby sh current limit v stby = 0.5 v 11 - 50 ma i stby load current - 0.1 - 10 ma v stby liner line regulation 6 v < v bat <18 v -25 - +25 mv v stby loadr load regulation 0.1 ma < i stby < 10 ma -25 - +25 mv
electrical characteristics L9758 18/29 doc id 14273 rev 3 4.9 vsa, vsb, vsc, vsd tracking linear regulator 4.10 rst5 and rstl reset signals t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v, unless otherwise specified. table 15. vsa, vsb, vsc, vsd tracking linear regulator t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v, unless otherwise specified. symbol parameter test condition min. typ. max. unit v trk output voltage tracking accuracy 1 ma < i t1 < 50 ma, 6 v < v bat_sw < 18 v 1 ma < i t1 < 5 0ma, 4 v < v bat_sw < 6 v -7 -50 - 10 50 mv i trk sh current limit v tck = 4.75 v 51 - 100 ma c trk esr output load capacitor ceramic or tantalum 1 0 - 16 3 f m ctckmin esrmin minimum output capacitor for stability ceramic or tantalum 1 0 - 3 f rr trk ripple rejection f= 375 khz 26 - - db vdrop dropout voltage i load = 50ma - - 300 mv t tsd thermal shutdown vtck = 4.75v (current limitation) 165 - 185 c t hyst thermal hysteresis vtck = 4.75v (current limitation) 5 - 15 c i trk load current - 1 - 50 ma table 16. rst5 reset signals symbol parameter test cond ition min. typ. max. unit i rst5_h reset ?high? leakage current v rst5 = 5.15 v -3.0 - - a v rst5_l reset ?low? output voltage v dd5 = 4.5 v ire = 5 ma v dd5 = 1.0 v ire = 1 ma -- 0.4 0.4 v v fth_rst5 reset threshold decreasing v dd5 / t < 0 4.5 - v dd5 ? 0.2 v v rth_rst5 reset threshold increasing v dd5 / t > 0 4.5 - v dd5 ? 0.07 v v hy_rst5 reset threshold hysteresis -50--mv t act_rst5 reset activation out of tolerance duration - 15 - 25 s t del_rst5 reset delay 4.7 k < r ext < 47 k 1-10ms t err_rst5 reset delay accuracy r ext 1% -15 - +15 %
L9758 electrical characteristics doc id 14273 rev 3 19/29 4.11 ign and psu_en inputs t amb = -40 c to 125 c, v bat = v bat_sw = 5.5 to 26.5 v, unless otherwise specified. table 17. rstl reset signals symbol parameter test condition min. typ. max. unit i rstl_h reset ?high? leakage current v ddl = 5.15 v -3.0 - - a v rstl_l reset ?low? output voltage v ddl =5.0v ire=5ma v ddl =1.0v ire=1ma -- 0.4 0.4 v v fth_rstl reset threshold decreasing v ddl / t < 0, v prog3 =low 2.375 - v ddl ? 0.05 v v rth_rstl reset threshold increasing v ddl / t < 0, v prog3 =low 2.375 - v ddl ? 0.02 v v fth_rstl_o reset threshold decreasing v ddl / t < 0, v prog3 =open 3.13 - v ddl ? 0.05 v v rth_rstl_o reset threshold increasing v ddl / t < 0, v prog3 =open 3.13 - v ddl ? 0.02 v v hy_rstl reset threshold hysteresis -40--mv t act_rstl reset activation out of tolerance duration -15-25 s t del_rstl reset delay 1nf < c ext < 10nf; 4.7k < r ext < 47k 1- 10 ms t err_rstl reset delay accuracy r ext 1% -15 - +15 % table 18. ign and psu_en inputs symbol parameter test condition min. typ. max. unit v th_ign ign input threshold threshold @ ign pin 2 - 3.6 v v hys_ign ign input threshold hysteresis - 0.2 - 1.4 v r pd_ign ign pull-down resistor - 300 - 1100 k v th_psuen psu_en input threshold - 0.9 - 0.55* v stby v v hys_psuen psu_en input threshold hysteresis - 0.2 - 0.8 v r pd_psuen psu pull-down resistor - 50 - 230 k v ol_ignon ign_on ?low? output voltage iol=1ma 0.4 v r ign_ext ign external input resistance 10 50 k
electrical characteristics L9758 20/29 doc id 14273 rev 3 4.12 stby_ok signal table 19. stby_ok signal t amb = -40c to 125c, v bat = v bat_sw = 5.5 to 26.5v, unless otherwise specified. symbol parameter conditions min max units t h_stbyok vstanbyok threshold v stby / t <0 -8,5 -3,5 % t stbydly stby_ok filter time 15 25 s t stbyok stby_ok delay accuracy 10 60 s v ol_stbyok stby_ok low output voltage v stby =1v i stbyok =1ma 0.4 v
L9758 functional description doc id 14273 rev 3 21/29 5 functional description 5.1 general function the L9758 is equipped with 9 linear voltage regulator. a buck boost switch mode power supply as pre regulator for the 7 main regulators is used to reduce the power consumption in the system. two standby regulators can be used to bias the system on off-mode. this to regulator?s are equipped with a independent bandgap voltage re ference. the current consumption of these two linear regulators is specified with less than 120 a in off state. i these standby function is not used the current consumption on the battery can be reduced by not connecting the vbat. under this condition the device enters immediately in the run mode, the pin psu_ren will lost his function. the quiescent curr ent on the vbat_sw can be reduced to maximum 10 a with 12 v battery voltage in off mode. the main regulators can be activated with the ign input. with a external resistor higher than 10 kohm in series to the ign pin a battery compliant signal can be used. in the function block diagram a resistor value of 51 kohm is mention and a 100 nf capacitor for noise robustness on ign. 5.2 switching pre-regulator the switching pre-regulator is a buck or a buck-boost current control mode regulator. the optional boost operation for low battery conditions can be selected connecting external logic level low side nch fet and an external diode in series to the inductor. the external parts required to complete the switching regulator are an inductor, recirculation diode and input and output filtering capacitor. the compensation network is inside the device. with a constant switching frequency of 350 khz, the pre-regulator controls the output voltage (the voltage at the vb and fdbk pins) to the limits stated in the electrical characteristics table varying the duty cycle. the 350 khz are related to r ext = 10 k (see section 5.8 ). at low battery voltages, in buck configuration, the pre-regulator runs with the duty cycle up to 100%. in buck-boost configuration normally it runs at 350 khz but for a limited range of input voltage it could enter in pulse skipping mode to control the output voltage. a soft start function is implemented reducing the current limitation during the power-up phase. 5.3 vdd5, vddl and vc ore linear regulators the vdd5 output is a fully integrated low drop out regulator. the v ddl and v core supplies will be implemented via an external n-channel pa ss mos, with the control being internal to the ic. if the pass mos is not used, two low current (max 30ma) regulator are available connecting directly vddl_fdbk to vddl_d rv and vcore_fdbk to vcore_drv with a resistor divider.the output of the pre-regulator is used as the source of these supplies. v dd5 is a fixed 5v nominal output, while v ddl and v core are programmable.
functional description L9758 22/29 doc id 14273 rev 3 the v ddl voltage is selectable with the vprog3 pin: 2.5v if connected to gnd and 3.3v if is left open (an internal pull-up is present). v core voltage is programmable connecting an external resistor divider at the feedback pin (vcore_fdbk). once programmed to a value at power-up, this value cannot change during the power cycle. it is the intent that the system run at a single fixed value for v ddl and v core for the life of the product. all the linear regulators start with a controlled slew rate when the pre-regulated voltage reaches v ddl_enup threshold as indicated in the electr ical characteristics table. all the linear regulator are short circuit protected with a limited current. 5.4 tracking regulators four low drop-out tracking re gulators (vsa, vsb, vsc and vsd ) are supplied by the output of the switching pre-regulator. they track the output voltage of the vdd5 linear regulator with the accuracy as specified in t he electrical characteristic table. the vsa regulator also tracks an external vo ltage reference (track_ref pin) and the tracking voltage is selected by the ref_sel pin. if ref_sel is tied high (5v) then v trk_ref is tracked. if ref_se l is left open then v dd5 is tracked. there is an intern al pull-down on ref_sel. the tracking supplies are intended to drive loads that are external to the ecu so they are short circuit protected with the current limited. the outputs of the tracking regulators also withstand short circuit to the battery. a short circuit to gnd, continuous or intermi ttent on one tracking supply will not affect any other supply, including the preregulator output voltage v b . in addition to these requirements, all sensor supplies shall be capable of operating with up to a 15f load on the supply line. this load may be present during initial startup, or be applied after the supply has been powered up. in either case, the application of this load shall not cause the tracking regulators to be permanently disabled. vsb, vsc and vsd regulators can be disabled with vs_en pin. 5.5 vkam and vstby linear regulators these two outputs are fully integrated low quiescent current low drop out regulators. the input vbat is used as the source of these supplies. these outputs are operational during both standby and run mode; these are the only outputs operational during standby (v bat not present). the vkam regulator has two programmable leve ls: 1.0v (vprog1 pin connected to gnd) or 1.5v (if this pin is left open, an internal pull-up is present). the v stby regulator has two programmable levels: 2.6v (vprog2 pin connected to gnd) or 3.3v (if this pin is left open, an internal pull-up is present). the stby_ok pin indicates when the v stby is out of range (voltage below the threshold indicated in the electrical characteristic tabl e). once driven low it should stay low for a minimal amount of time allowing external circuitry to latch.
L9758 functional description doc id 14273 rev 3 23/29 5.6 reset monitors rst5 is the reset signal tied to the v dd5 supply. this is an open collector active low signal that pulls low when v dd5 is out of range. rstl is the reset signal for the v ddl supply. this is an open collector active low signal that pulls low when v ddl is out of range. rst5 and rstl are also driven low when stby_ok pin is driven low, regardless of the status of v dd5 and v ddl . reset delay is the time duration from when the output (v dd5 or v ddl ) is within range to when the reset pin (rst5 or rstl) is released. rst5 and rstl use separate timers. this delay is programmable via an external resistor connected to rst_tim pin. a value of 4.7 k corresponds to 1 ms and 47 k to 10 ms. all values in between are linear approximated. the timer delay is common however the attack and release times are only dependant on the condition of the respective supplies (v dd5 or v ddl ). 5.7 thermal protection the tracking regulators incorporate thermal limit with shutdown. when the junction temperature reaches the shutdown threshold, if there is a tracking regulator in current limitation, it switches off and all the other regulators stay on. when the temperature decrease the regulator restarts. the over temperature shutdown has an hysteresis to avoid thermal pumping. 5.8 reference current the L9758 provides a dc voltage at the rext pin. an external resistor to ground creates a reference current which is mirrored internally for use in the device. the reference current is used to supply all the analog blocks and to charge and discharge an integrated capacitor to generate a 5 mhz clock for the switching functionality. figure 3. current reference generator the circuit is designed for a 10 k resistor. for all affected para meters, this resistor value is mentioned in the electrical characteristics section. - + v ref + - r ext iref iref - + v ref + - r ext iref iref
operating modes L9758 24/29 doc id 14273 rev 3 6 operating modes there are two modes of operation of the power supply: standby and run mode. however during run mode, there are three input voltage regions: low voltage, normal voltage and high voltage. a brief definition and description of each of these operating regions is described below. 6.1 standby mode standby mode is defined by the following conditions: vbat is within the required voltage range vbat_sw may or may not be present ign is in the off state psu_en is not asserted by the microprocessor during standby mode, all func tions are shutdown except t he two standby supplies, vkam and vstby, and the circuitry monitoring ign and psu_en. during standby mode, current consumption is minimized. the standby functions are powered from vbat. there is no currents drawn from vbat_sw or any other input except those required to perform the standby functions. outputs, other than ign_on are disabled, sourcing nor sinking current. 6.2 run mode run mode is defined by the following conditions: vbat is within the required range vbat_sw is within the required range either ign is in the run state and/or psu_en is in the active state during run mode, all functions can be enabled. all functions listed above, with the exception of the standby functions, are powered by vbat_sw. if vbat is not present, the circuit is fully running with the exception of psu_en and the standby functions (vkam and vst by). in this condition the en try into the run mode can only be performed by the ign pin and the circuit is kept running until ign pin is in pulled low. 6.2.1 entry into run mode run mode is entered when at least one of the two signals ign_sw or psu_en goes in the active state. these two signals may be applied in any order or simultaneously. when the ign input is valid, the acti ve low ign_on signal is asserted. the design of vdd5, vddl and vcore regulators limits the slew rate of the output voltages during the start-up as indicated in the electrical characteristic table and ensures that v dd5 is always greater than v ddl and v core . as indicated in figure 4 , the switching regulator starts first with soft start control or reduced current limitation. when the vb voltage reaches the vddl_enup threshold all the linear regulator start with co ntrolled slew-rate. the slew-rate co ntrol is done cont rolling the slew
L9758 operating modes doc id 14273 rev 3 25/29 rate of the common voltage reference so the slew is different for each regulator because all start together and reach the steady-state at the same time but with different voltage levels. 6.3 power down the power down sequence starts when both ign and psu_en signal are low. in this phase there is no control of the linear regulator output voltages. the falling slew-rate is defined from load currents and load capacitors. a voltage comparator controls vddl voltage and ensures that the vddl supply voltage will drop below 2v before initiating a new power-up sequence. figure 4. power up/down sequence 6.4 low voltage operation when L9758 is up and running it is fully operational with the vbat and vbat_sw pin voltages down to v lv i _ l ow . when L9758 is up and running and the supply voltages are less than 5.5v and are greater or equal to v lv i _ l ow if the boost option is used the device is fully operational. if only the buck regulator is used the L9758 operates as follow: switching regulator runs at 100% duty cycle vkam and vstby regulators are fully operational vddl fully operational vcore fully operational vdd5 out of range with output voltage no less than 3.2v tracking regulators out of range with output voltages no less than 3.2v reset monitor rst5 and rstl fully operational, with reset at rst5 pin in allowed ign or psu_en vb vth_start vdd5 vddl inductor current soft start slew rate control current limitation vcore rst5 rstl
operating modes L9758 26/29 doc id 14273 rev 3 6.5 high voltage operation the L9758 is fully operational during jump start when the battery is temporarily replaced with a higher voltage source to aid starting the engine (26.5v for 1 minute). the L9758 is fully operational during positive battery transient such as load dump (40v maximum voltage with durations of up to 400ms).
L9758 package information doc id 14273 rev 3 27/29 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 5. powerso-36 mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.60 0.1417 a1 0.10 0.30 0.0039 0.0118 a2 3.30 0.1299 a3 0 0.10 0.0039 b 0.22 0.38 0.0087 0.0150 c 0.23 0.32 0.0091 0.0126 d 15.80 16.00 0.6220 0.6299 d1 9.40 9.80 0.3701 0.3858 e 13.90 14.5 0.5472 0.5709 e1 10.90 11.10 0.4291 0.4370 e2 2.90 0.1142 e3 5.80 6.20 0.2283 0.2441 e 0.65 0.0256 e3 11.05 0.4350 g 0 0.10 0.0039 h 15.50 15.90 0.6102 0.6260 h 1.10 0.0433 l 0.8 1.10 0.0315 0.0433 n 10? (max) s 8? (max) note: ?d and e1? do not include mold flash or protusions. - mold flash or protusions shall not exceed 0.15mm (0.006?) - critical dimensions are "a3", "e" and "g". powerso-36 0096119 c
revision history L9758 28/29 doc id 14273 rev 3 8 revision history table 20. document revision history date revision changes 12-dec-2007 1 initial release. 17-nov-2010 2 updated section 1: pins configuration . updated figure 2: functional block diagram . updated section 3: operating conditions . updated table 7: general dc characteristics and table 12: vcore linear regulator . added section 5.1: general function . updated section 5.2: switching pre-regulator , section 5.6: reset monitors and section 5.8: reference current . updated section 5.3: vdd5, vddl and vcore linear regulators on page 21 . 23-nov-2010 3 update ta b l e 1 0 , ta b l e 1 1 , ta bl e 1 2 , ta bl e 1 3 and ta bl e 1 4 .
L9758 doc id 14273 rev 3 29/29 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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